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K. Bult and G. J. G. M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, 1990, pp. 1379-1384. http://dx.doi.org/10.1109/4.62165

has been cited by the following article:

• TITLE: On the Operation of CMOS Active-Cascode Gain Stage

  AUTHORS: Yun Chiu

  KEYWORDS: CMOS Operational Amplifier; Gain Enhancement; Active Cascode; Regulated Cascode; Gain Boosting; Pole- Zero Pair; Doublet; Slow Settling

  JOURNAL NAME: Journal of Computer and Communications, Vol.1 No.6, November 26, 2013

  ABSTRACT: An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.