"
A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer"
written by Kenichi Ohhata, Kaihei Hotta, Naoto Yamaguchi, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Yuuki Sonoda,
published by
Circuits and Systems,
Vol.8 No.1, 2017
has been cited by the following article(s):
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[1]
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A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2018
DOI:10.1109/TVLSI.2018.2827943
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[2]
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900-MHz, 3.5-mW, 8-bit pipelined subranging ADC combining flash ADC and TDC
2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT),
2017
DOI:10.1109/RFIT.2017.8048272
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