NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.net/journal/cs
E-mail: [email protected]

Citations

"NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates"
written by Ali Dadashi, Omid Mirmotahari, Yngvar Berg,
published by Circuits and Systems, Vol.7 No.8, 2016

has been cited by the following article(s):

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[4]	Ultra-Low-Voltage and Energy-Efficient Circuit Techniques for iOTs
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[5]	A 4: 1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology
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[6]	A 1‐bit full adder using CNFET based dual chirality high speed domino logic
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[7]	Low leakage domino logic circuit for wide fan‐in gates using CNTFET
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[8]	Low leakage domino logic circuit for wide fan-in gates using CNTFET
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[9]	Ultra Low Voltage Logic Design For High-Speed Processing
	2017

[1]	The Effect of Noise Robustness on Domino Using Silicon Nano Materials Silicon, 2024 DOI:10.1007/s12633-024-02854-8

[2]	Impact of Silicon Stacked Transistors on Nano Scale Domino Logic Silicon, 2022 DOI:10.1007/s12633-021-01629-9

[3]	A 1‐bit full adder using CNFET based dual chirality high speed domino logic International Journal of Circuit Theory and Applications, 2020 DOI:10.1002/cta.2714

[4]	Low leakage domino logic circuit for wide fan-in gates using CNTFET IET Circuits, Devices & Systems, 2019 DOI:10.1049/iet-cds.2018.5135

[5]	A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology International Journal of Electronics, 2019 DOI:10.1080/00207217.2019.1663942

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