Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards

Circuits and Systems

ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"Efficient FPGA implementation of AES 128 bit for IEEE 802.16e mobile WiMax standards"
written by P. Rajasekar, Dr. H. Mangalam,
published by Circuits and Systems, Vol.7 No.4, 2016

has been cited by the following article(s):

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[1]	Secure Video and Telemetry FPGA Architecture For UAVs 2024 9th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2024 DOI:10.1109/SEEDA-CECNSM63478.2024.00021

[2]	A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application Electronics, 2021 DOI:10.3390/electronics10162023

[3]	Design and implementation of power and area optimized AES architecture on FPGA for IoT application Circuit World, 2020 DOI:10.1108/CW-04-2019-0039

[4]	10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform Electronics, 2020 DOI:10.3390/electronics9101665

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