A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits

ISSN Print: 2153-1285
ISSN Online: 2153-1293
www.scirp.net/journal/cs
E-mail: [email protected]

Citations

"A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits"
written by Tarun Kumar Gupta, Kavita Khare,
published by Circuits and Systems, Vol.4 No.2, 2013

has been cited by the following article(s):

[1]	Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits
	INTELLIGENT AUTOMATION AND …, 2023

[2]	Robust Design Methodologies Under Performance Variations for More Than Moore Technologies: CNFETs & 3DICs
	2022

[3]	Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile
	2018

[4]	A Novel High-Performance Lekage-Tolerant, Wide Fan-In Domino Logic Circuit in Deep-Submicron Technology
	Circuits and Systems, 2015

[5]	A High Speed Leakage Tolerant Domino Techniques
	PLM Yuvaraja - techscripts.org, 2014

Top

[1]	Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits Intelligent Automation & Soft Computing, 2023 DOI:10.32604/iasc.2023.028758

[2]	Challenges in Low Power VLSI Design: A Review 2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA), 2021 DOI:10.1109/ICECA52323.2021.9676055