Dr. Randy W. Mann

Booz Allen Hamilton, USA

Email: [email protected]

Qualifications

2010 Ph.D., University of Virginia, Electrical Engineering

1979 B.Sc., University of North Carolina, Chemistry

Publications(selected)

1. Mann, R. W. (2026). Sram physical unclonable function with improved bit error rate (U.S. Patent Application No. 19/347,012). U.S. Patent and Trademark Office.
2. Zhao, M., Shen, H., & Mann, R. W. (2025). Semiconductor fin with divots, transistor including the semiconductor fin, memory cell including the transistor, and associated methods (U.S. Patent Application No. 18/448,467). U.S. Patent and Trademark Office.
3. Mann, R. W., Paul, B. C., & Frougier, J., et al. (2022). Structures and SRAM bit cells integrating complementary field-effect transistors (U.S. Patent No. 11,309,319). U.S. Patent and Trademark Office.
4. Zhao, M., Mann, R. W., & Parihar, S., et al. (2021). SRAM bit cells formed with dummy structures (U.S. Patent No. 11,037,937). U.S. Patent and Trademark Office.
5. Mann, R. W., Paul, B. C., & Frougier, J., et al. (2020). Structures and SRAM bit cells integrating complementary field-effect transistors (U.S. Patent No. 10,818,674). U.S. Patent and Trademark Office.
6. Mann, R. W., Zhao, M., & Kwon, O. S., et al. (2020). Bias-dependent variation in FinFET SRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(5), 1339–1343.
7. Mann, R. W., & Paul, B. C. (2019). Static random access memory cells with arranged vertical-transport field-effect transistors (U.S. Patent Application No. 15/983,627). U.S. Patent and Trademark Office.
8. Mann, R. W., & Paul, B. C. (2019). Dual port vertical transistor memory cell (U.S. Patent No. 10,439,064). U.S. Patent and Trademark Office.
9. Mann, R. W., & Paul, B. C. (2019). Six-transistor (6T) SRAM cell structure (U.S. Patent No. 10,403,629). U.S. Patent and Trademark Office.
10. Zhang, X., Zang, H., Thankalekshmi, R. R., & Mann, R. W. (2019). Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails (U.S. Patent No. 10,332,897). U.S. Patent and Trademark Office.
11. Song, Y., Mann, R., & Xie, S., et al. (2019). Direct insight to SRAM array devices in advanced FinFET nodes by large scale ultra-fast in-situ characterization. In 2019 IEEE 11th International Memory Workshop (IMW) (pp. 1–4). IEEE.
12. Mann, R. W., Zhao, M., & Parihar, S., et al. (2019). An extrinsic device and leakage mechanism in advanced bulk FinFET SRAM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(8), 1888–1894.
13. Zang, H., & Mann, R. W. (2019). Sram structure with alternate gate pitches (U.S. Patent Application No. 15/689,934). U.S. Patent and Trademark Office.
14. Zhang, X., Zang, H., Thankalekshmi, R. R., & Mann, R. W. (2018). Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails (U.S. Patent No. 10,163,914). U.S. Patent and Trademark Office.
15. Zang, H., Mann, R. W., & Paul, B. C. (2018). Cross couple structure for vertical transistors (U.S. Patent No. 10,109,637). U.S. Patent and Trademark Office.
16. Yanping, S., Zang, H., & Lo, H. C., et al. (2018). Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method (U.S. Patent No. 10,068,902). U.S. Patent and Trademark Office.
17. Paul, B. C., Jacob, A. P., & Taylor, W., et al. (2018). A retrospective view on the technology evolution to support low power mobile application. Journal of Low Power Electronics, 14(3), 374–392.
18. Gautam, A., Mann, R. W., & McMahon, W., et al. (2018). Method, apparatus, and system for targeted healing of write fails through bias temperature instability (U.S. Patent No. 9,916,212). U.S. Patent and Trademark Office.
19. Gautam, A., Mann, R. W., & McMahon, W., et al. (2017). Methods, apparatus, and system for global healing of write-limited die through bias temperature instability (U.S. Patent Application No. 15/615,660). U.S. Patent and Trademark Office.
20. Wu, X., Liu, B., & Mann, R. (2017). Hardmask for a halo/extension implant of a static random access memory (SRAM) layout (U.S. Patent No. 9,761,594). U.S. Patent and Trademark Office.

Profile Details

https://randywmann.com/
https://scholar.google.com/citations?user=zcQTi6UAAAAJ&hl=en
https://www.researchgate.net/profile/Randy-Mann

WOS ResearcherID: OOM-1081-2025